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Applied Materials and Intel expand AI chipmaking collaboration at epic center
Applied Materials and Intel will co-develop next-gen transistors and Foveros 3D stacking at the $4 billion EPIC Center to compress AI chip development timelines.
Applied Materials and Intel are expanding their chipmaking partnership at the EPIC Center in Silicon Valley, a move that ties Intel's Oregon research campus directly into a $4 billion facility designed to compress semiconductor development timelines. The collaboration, announced October 6, 2026, targets next-generation transistors, interconnects, and advanced packaging specifically for AI workloads, where performance-per-watt and thermal management have become critical gating factors.
The work focuses heavily on Foveros-based 3D stacking technology. Teams aim to improve interconnect density, power delivery, and thermal performance - three variables that directly determine how many AI compute cores can operate in a single package without throttling. Applied President and CEO Gary Dickerson said the partnership would "shorten development cycles" and bring AI-relevant technologies to market faster.
The EPIC Center's scale and timeline
Applied Materials launched the EPIC Center in 2023 with $4 billion in capital investments over seven years. The facility includes 180,000 square feet of cleanroom space and targets $25 billion in R&D investments across its first decade, supported in part by the CHIPS and Science Act. Founding partners included Intel, AMD, IBM, Micron, Nvidia, Samsung, TSMC, and Western Digital - a roster that spans the entire chipmaking supply chain.
Intel CEO Lip-Bu Tan emphasized the practical stakes for AI computing, pointing to the twin demands of performance and power efficiency. Dr. Prabu Raja, president of Applied's Semiconductor Products Group, highlighted the complexity of modern chipmaking roadmaps and the need for tighter integration between equipment makers and chip designers to avoid multi-year delays between process node advancements.
Why advanced packaging matters for AI workloads
Traditional transistor scaling no longer delivers the performance gains it once did. Advanced packaging - stacking chiplets vertically rather than laying them side-by-side - has become the primary lever for improving AI chip throughput. Foveros, Intel's 3D stacking architecture, lets designers place logic, memory, and I/O tiles in a single package with shorter data paths and lower power draw than conventional interposer approaches.
The Applied Materials-Intel collaboration embeds equipment engineering directly alongside process development, reducing the lag between lab discovery and fab deployment. For operations teams and process engineers, this model shortens the feedback loop that typically separates tool qualification from high-volume manufacturing.
Why this matters for process and operations professionals
When equipment vendors and chipmakers co-locate R&D inside a facility built for rapid iteration, the timelines for new process qualifications compress. Process engineers and operations managers should expect faster transitions from pilot-line demonstrations to production-ready recipes, particularly for heterogeneous integration and hybrid bonding steps. The EPIC Center's multi-company model also means cross-pollination across competing roadmaps - a dynamic that rewards teams who can adapt process controls quickly as packaging standards evolve. For professionals managing fab operations or process development, understanding how these collaborative R&D hubs influence tool qualification cycles is becoming as important as tracking node transitions themselves. Courses like AI Process Engineering Courses and AI Process Innovation Courses address the shift toward data-driven process control that facilities like EPIC are built to accelerate.