AI news ·
Harmonic Expands Aristotle Into Software and Chip Verification
Harmonic now uses its AI to mathematically verify C code and Verilog chip designs for safety-critical systems.
Harmonic has extended its Aristotle model to cover verification of C software and Verilog chip designs. The move brings formal verification capabilities into two domains where correctness is critical and defects carry significant operational or safety risk.
The system uses AI to assist the formal verification process. The underlying approach aims to reduce defects by mathematically proving properties of a design or codebase, rather than relying solely on testing. The company notes that proofs, specifications, and any automatically generated fixes must remain independently auditable to maintain trust in the verification outcome.
This capability is relevant across sectors that depend on reliable software and hardware, including medical devices, legal-compliance systems, scientific instrumentation, and IT infrastructure where design errors can lead to costly failures.