TIER IV, the company behind Autoware, the open-source autonomous driving software stack, has joined a Japan Science and Technology Agency (JST) research program to develop an open-source AI chip design for Level 4 autonomous driving. The company will design the logic for a system-on-chip (SoC) tailored to run end-to-end autonomous driving AI models and release the design files, compiler, and toolchain publicly.
The work falls under JST's Next-Generation Edge AI Semiconductor Research and Development Program. TIER IV is developing the chip's logic design in cooperation with a University of Tokyo research team led by Professor Yoshihiro Kawahara, which is investigating use-case-driven chip architectures for physical AI. The goal is to give semiconductor makers an open foundation they can build on to commercialize SoCs for autonomous vehicles.
The case for a specialized chip
Level 4 autonomous driving requires AI models to run continuously in real time, in real-world conditions. General-purpose GPUs powered much of AI's rapid evolution, but they carry power and control overhead that proves costly in vehicles. TIER IV said its dedicated architecture simplifies the complex control mechanisms needed for general-purpose computing and instead streamlines the repeated processing patterns common in Transformer models, such as matrix multiplication and the attention mechanism.
The design targets performance per watt across the whole system, not just peak chip throughput. Data needed for model execution will be placed and reused on the chip, reducing external memory transfers and power consumption. The architecture is intended to scale from embedded devices at a few watts to in-vehicle electronic control units at a few tens of watts.
Open source approach
Rather than optimizing for a single AI model, TIER IV is adopting an intermediate representation layer called the Tensor Operator Set Architecture (TOSA). AI models built in frameworks such as PyTorch get converted into this common TOSA form, then optimized and compiled before executing on the chip. The layering decouples software frameworks from hardware, so future model changes can be handled with compiler and runtime updates instead of a full chip redesign.
The company will open-source the chip's logic design, compiler, and related toolchain, extending the same collaborative model that drives Autoware development. That transparency extends to verification: TIER IV will use formal verification techniques to mathematically confirm numerical consistency after the transformations that occur between model format and chip execution, such as quantization and rounding.
Why this matters for IT and development teams
For developers, the project's TOSA-based approach helps isolate AI models from hardware specifics. An open source compiler and toolchain for autonomous driving inference could be adapted to other hardware, and the publicly inspectable design is relevant for safety-in-critical software work. The open-source toolchain also lowers the barrier for research teams that want to build custom silicon without starting from a blank sheet.
For those focused on research, the project explicitly ties into academic exploration of AI hardware. The University of Tokyo's involvement validates the shift from general-purpose parts to function-specific designs, and the public release of design assets offers a reference platform for studying practical AI chip architecture.
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