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AI agent for hardware engineers

Layout Design Rule Review Agent

Catch layout errors before fabrication with a checked list that closes issue by issue

Layout Design Rule Review Agent: what goes in, what the agent does and what you get

What it does

A board with a split ground plane under a fast signal can pass the basic design rule check and fail at test. This agent reads the design rule check output and layout notes, then goes beyond them. It checks high-speed nets for length matching, return paths and impedance, power nets for trace width and current, and hot parts for copper and via count. It follows the manufacturer's rules and the part datasheet layout guidance. It writes a numbered issue list with the net and location, and rechecks after each revision of the layout. The designer fixes the issues and approves release to fabrication. Edge case: a clearance violation is an intentional test point shape, so the agent asks before flagging it again.

How it works

Follow the arrows from top to bottom. The orange dashed arrow is the loop: when a check fails, the agent goes back and tries again.

Start and resultWhat it doesA check on its own workWaits for your OKGoes back and retries
ApprovedYes, continueApprovedNo 1 STARTS WHEN Layout revision submitted for review 2 USES A TOOL Read the rule check report and layout data 3 DOES Check high-speed nets for length, return path andimpedance 4 DOES Check power nets for width, current and decouplingplacement 5 DOES Check thermal copper and vias on hot parts 6 DOES Write the numbered issue list ranked by risk 7 YOU APPROVE Designer reviews issues and marks acceptedexceptions 8 USES A TOOL Designer revises layout; agent reads the new files 9 CHECKS THE RESULT Are all high and medium issues closed with no newones? If not: rerun all checks on the new revision and updatethe list. Back to step 3. 10 YOU APPROVE Designer approves release to fabrication 11 RESULT Review record and fabrication release notes
Read the steps as a list
  1. Layout revision submitted for review
  2. Read the rule check report and layout data
  3. Check high-speed nets for length, return path and impedance
  4. Check power nets for width, current and decoupling placement
  5. Check thermal copper and vias on hot parts
  6. Write the numbered issue list ranked by risk
  7. Designer reviews issues and marks accepted exceptionsThe agent waits here for your OK.
  8. Designer revises layout; agent reads the new files
  9. Are all high and medium issues closed with no new ones?If not: rerun all checks on the new revision and update the list. Back to step 3.
  10. Designer approves release to fabricationThe agent waits here for your OK.
  11. Review record and fabrication release notes

How it decides

It ranks issues by risk of board failure and treats any open high-risk issue as a blocker.

  • Block release on any open high-risk issue
  • Check that every high-speed signal has a continuous reference plane
  • Flag power traces carrying over 1 A that are under 0.5 mm
  • Record accepted exceptions with a reason

Make it yours

Every agent is a starting point. You choose these settings for your own situation.

  • Rule sets by interface (default per vendor guidelines)
  • Minimum trace width for current
  • Severity labels
  • Manufacturer capability limits
  • Exceptions list

What keeps you in control

It always asks you first

  • Designer approves exceptions
  • Designer approves release to fabrication

Hard limits

  • Never release files to a fabricator
  • Never delete an issue without the designer's note

It stops when

  • Done: no open high or medium issues remain
  • Stop: a stackup change is needed and the layout is reopened

Set it up

We guide you through the set-up, step by step

Members get the full set-up guide for this agent. No technical skills needed: you copy, paste and upload.

10 minto set it up in your AI
5 AIsChatGPT, Claude, Copilot, Gemini, Grok
  • One set of instructions to paste into your AI, with the clicks for ChatGPT, Claude, Microsoft 365 Copilot, Gemini and Grok
  • The agent then walks you through connecting your own data, one source at a time
  • A downloadable copy with the flow chart, the rules and the full guide
Get access to this agent

An example run

What happensRevision C of a 6-layer board had 31 issues. Four were high: an 8 mm DDR trace pair mismatch of 0.9 mm, a split under a clock, a 0.3 mm trace carrying 1.4 A, and a missing thermal via array. The designer fixed these in revision D. The recheck closed three but raised a new clearance error from a moved via, so the check failed. Revision E passed and the designer released to fabrication.

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