Astera Labs opens Israel design center to boost AI connectivity development
Astera Labs is expanding its global engineering footprint with a new R&D design center in Israel, adding offices in Tel Aviv and Haifa. The hub will focus on next-generation AI fabrics and memory solutions aimed at removing data, network, and memory bottlenecks in training and inference workflows.
The operation will be led by Guy Azrad, senior vice president of engineering and general manager of Astera Labs Israel, alongside Ido Bukspan, vice president of ASIC engineering. The mandate: build at-scale connectivity that keeps pace with modern GPU and CPU clusters.
What the Israel design center will build
- Scale-up fabrics for high-bandwidth connectivity across data center topologies.
- Deeper integration of Astera Labs' Intelligent Connectivity Platform, spanning CXL, Ethernet, NVLink Fusion, PCIe, and UALink with the COSMOS software suite.
- End-to-end chip design: from architecture and RTL through verification, physical implementation, and production.
- System and software development targeting inference-era requirements such as memory pooling, low-latency links, and deterministic performance.
Why it matters for AI infrastructure teams
Compute is scaling faster than I/O and memory capacity. The work coming out of Tel Aviv and Haifa targets that gap-more bandwidth per node, lower fabric latency, and smarter memory access at cluster scale.
- Faster GPU-to-GPU and CPU-GPU communication for training and inference pipelines.
- Memory pooling and expansion via CXL for better utilization and larger model contexts.
- Improved congestion control, QoS, and observability across mixed-protocol fabrics.
- Better power and cost efficiency at rack and pod levels through balanced interconnect design.
Leadership with deep networking and silicon experience
Guy Azrad previously served as vice president of chip design engineering at Google, leading silicon programs for compute. Before that, he held senior roles at Marvell, including senior vice president of the global Ethernet switching division, and has overseen multiple generations of high-performance networking SoCs and large-scale design teams.
Ido Bukspan brings more than two decades building data center interconnects at Mellanox Technologies and NVIDIA, where he led development across InfiniBand, Ethernet, and NVLink. He most recently served as CEO of Pliops, focusing on data acceleration and key-value cache technologies.
Quotes
"We're building an engineering team with a strong focus on execution, covering hardware, silicon, and software solutions, to support the growing adoption of Astera Labs' Intelligent Connectivity Platform," Azrad said. "With offices in Tel Aviv and Haifa, the new Israel design center will look to tap into the region's world-class engineering talent to focus on the full chip design flow-from architecture through production, including software and system design for cutting-edge AI fabrics and emerging inference applications."
"Israel has been defining networking innovation for decades, from those formative years when we were proving what was possible to today's AI-driven transformation," Bukspan said. "I see the same drive, the same intensity to deliver highly performant connectivity solutions at Astera Labs. Together, we're taking AI connectivity to the next level. Come join us."
Ecosystem and hiring
Astera Labs frames this as a long-term investment in Israel's semiconductor ecosystem, with plans to collaborate with universities and the local venture community. The company is actively recruiting engineers across Tel Aviv and Haifa to support its AI connectivity platform.
If you work in silicon, systems, or low-level software, expect opportunities that touch the full stack-from link layer and memory coherence to firmware, drivers, and performance engineering.
Tech stack highlights
The Intelligent Connectivity Platform integrates established and emerging data center standards. For background on a few of them, see CXL and the new UALink consortium efforts. Together with Ethernet, PCIe, and NVLink Fusion, the goal is consistent scaling across nodes, racks, and pods with software-aware orchestration via COSMOS.
What engineers can expect to work on
- ASIC/SoC architecture, RTL design, verification, physical design, and silicon validation.
- High-speed interfaces, SerDes, packaging considerations, and signal/power integrity.
- Memory systems (CXL), cache coherence, and data movement across heterogeneous accelerators.
- Firmware, drivers, performance modeling, congestion control, and telemetry integrated with COSMOS.
- System bring-up, interoperability across protocols, and reliability engineering at cluster scale.
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