Cadence and NVIDIA Accelerate Power Analysis for Billion-Gate AI Designs
Cadence has made a significant advancement in power analysis for pre-silicon designs through a close partnership with NVIDIA. By leveraging the Cadence® Palladium® Z3 Enterprise Emulation Platform combined with the new Cadence Dynamic Power Analysis (DPA) App, the companies have achieved hardware-accelerated dynamic power analysis of billion-gate AI designs. This analysis covers billions of cycles within hours and achieves up to 97% accuracy.
This breakthrough allows semiconductor and systems developers focused on AI, machine learning (ML), and GPU-accelerated applications to design more energy-efficient systems and speed up their time to market.
Overcoming Limitations of Conventional Power Analysis
Modern semiconductors are extremely complex and require massive computational resources to analyze power consumption accurately under real-world conditions. Traditional power analysis tools struggle to scale beyond a few hundred thousand cycles without demanding excessive time.
Working closely with NVIDIA, Cadence has addressed these challenges by combining hardware-assisted power acceleration with parallel processing innovations. This approach enables precise power analysis over billions of cycles early in the design process, something that was previously unattainable.
Insights from Industry Leaders
Dhiraj Goswami, corporate vice president and general manager at Cadence, highlighted the achievement: “This project redefined boundaries, processing billions of cycles in as few as two to three hours. This empowers customers to confidently meet aggressive performance and power targets and accelerate their time to silicon.”
Narendra Konda, vice president of Hardware Engineering at NVIDIA, added, “As AI infrastructure evolves, engineers require advanced tools to design energy-efficient solutions. Combining NVIDIA’s accelerated computing expertise with Cadence’s EDA leadership advances hardware-accelerated power profiling for more precise efficiency.”
How the Palladium Z3 Platform Enhances Design Efficiency
The Palladium Z3 Platform, using the DPA App, provides accurate power consumption estimates under realistic workloads. This capability allows teams to verify functionality, power usage, and performance before tapeout, when design optimizations can still be made.
Early power modeling is especially valuable for AI, ML, and GPU-accelerated designs. It helps improve energy efficiency while avoiding delays caused by over- or under-designed chips.
Integrated into Cadence’s analysis and implementation flow, Palladium DPA supports power estimation, reduction, and signoff throughout the entire design cycle. This integration leads to more efficient silicon and system designs, giving developers a competitive edge.
Additional Resources
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