The AI Chip Arms Race: How China Built Its Own "Manhattan Project"
China has a working prototype of an extreme ultraviolet (EUV) lithography machine in a Shenzhen lab. It fills almost a factory floor, generates EUV light, and was assembled by engineers who previously worked at ASML. It hasn't produced functional chips yet-but the milestone is real.
This effort ties into a six-year national push for semiconductor self-sufficiency, overseen at the highest levels of government and coordinated across firms and institutes. Think centralized strategy, fast hiring, and heavy secrecy. Internally, some participants used false identities, and entire teams operated in isolation.
What they actually built
EUV machines use 13.5 nm light to etch extremely small features on wafers. ASML is still the only company shipping working systems at scale, supported by Carl Zeiss optics that set the precision standard. China's prototype is larger and rougher, designed to drive higher power, with optics still lagging.
Progress came from three levers: reverse-engineering older tools, sourcing parts from secondary markets and intermediaries, and recruiting ex-ASML talent. A dedicated group of about 100 new grads filmed every teardown and rebuild to speed learning. Bonuses were tied to successful reassembly.
Why EUV is hard
The light source must be extremely bright and clean, or you get contamination, low throughput, and poor yields. The optical path needs Zeiss-level accuracy across mirrors and stages measured in nanometers. Every subsystem-metrology, vibration control, vacuum, pellicles-has to cohere at once.
ASML spent nearly two decades getting to commercial output. China's team benefits from the fact that EUV already exists, so the path is clearer-but still brutal.
Who's running point
Huawei is a central coordinator across design, fabrication, and integration. Work practices are intense: on-site sleeping, strict communication controls, and compartmentalization. CIOMP (Changchun Institute of Optics, Fine Mechanics and Physics) leads optics with aggressive pay, grants, and timelines.
Key hires reportedly include former ASML leaders in light source tech with active patent activity. This shortens cycles on the most stubborn bottlenecks.
Export controls, supply chains, and the clock
U.S. pressure blocked EUV sales to China and tightened access to advanced DUV gear to keep China at least one generation behind. Enforcement has targeted loopholes and gray channels. Despite this, a thriving secondhand market has fed parts and subassemblies into the project.
Public guidance suggests operational chip output might land around 2028-2030 if optics and source issues close. That's faster than many expected. It's not parity with ASML, but it narrows the gap materially.
- ASML EUV basics: EUV lithography
- Policy context: U.S. export controls on semiconductors
Why this matters if you build or run AI systems
GPU and accelerator availability
If China hits working EUV, it unlocks smaller nodes and more domestic supply for NPUs, AI accelerators, and memory. That can shift pricing and lead times globally. Even partial success (advanced DUV plus packaging) can boost performance-per-watt for local vendors.
Architectural diversity
Expect more designs optimized for domestic constraints: custom AI cores, chiplets, and memory-heavy architectures. Software stacks will fragment further-think alternative graph compilers, toolchains, and runtime libraries tuned to non-NVIDIA hardware.
- Plan for portability: ONNX, TVM, MLIR, and backends for diverse accelerators.
- Invest in quantization and sparsity to stretch older nodes and mixed-precision silicon.
- Prepare kernels that can target NPUs, not just CUDA.
Packaging and yield workarounds
Advanced packaging-2.5D, 3D stacking, HBM integration-can offset node disadvantages. Even without perfect EUV, smart packaging plus DUV can ship competitive parts for AI inference. Watch for local supply of photoresists, pellicles, and metrology to reduce yield loss.
Compliance and procurement
- Inventory where your infra or vendors touch restricted tech. Keep a live SBOM for hardware, not just software.
- Expect sudden rule updates and license shifts. Build dual-approved vendor lists by region.
- Audit data center locations, cloud GPU pools, and colocation partners for export-control exposure.
Inside the program: tactics and constraints
China's teams reportedly used salvaged ASML parts, modules from Nikon/Canon via intermediaries, and constant teardown video to accelerate learning. Auctions for older fab equipment became a supply channel. Some suppliers deny direct knowledge; intermediaries obscure end buyers.
Optics remain the biggest blocker given Zeiss's dominance. CIOMP's early EUV integration is a step, but throughput and defectivity must catch up. Analysts point to a "good enough" light source with low contamination as the next threshold.
Timeline markers to watch
- Stable EUV light source power and uptime metrics.
- Domestic mirror quality and stage precision reports from CIOMP and partners.
- Trial wafers showing repeatable yields at advanced nodes, even small volumes.
- Evidence of local pellicle, resist, and metrology ecosystems maturing.
What you can do now
- Abstract your AI workloads from specific hardware. Target multiple backends early.
- Track BOM lineage for accelerators you buy or rent. Document export-control assumptions.
- Pilot compilers that retarget graphs automatically (e.g., TVM, IREE, XLA variants).
- Model cost/perf on older nodes plus packaging so you're not dependent on one supplier's cadence.
The headline is simple: China hasn't matched ASML, but the gap is getting smaller faster than expected. For IT and dev teams, the smart move is portability, compliance readiness, and a procurement plan that assumes more silicon diversity ahead.
If you want to keep skills current across fast-moving AI stacks, see curated paths by role at Complete AI Training.
Your membership also unlocks:
