Omiya Hassan, assistant professor in Boise State University's Department of Electrical and Computer Engineering, received nearly $500,000 from the National Science Foundation to develop AI chips that process data using both electricity and light. The three-year project targets the energy bottleneck created when data shuttles between memory and processor, a problem that grows more expensive as AI models scale up.
The project, titled "3D Integrated Parallel Fabrics enabling Layered Opto-electronic Processors for Near-memory AI Computing" (3DPFLOPS), combines light-based computing, 3D-stacked chip architecture, and smart workload scheduling into a single design. The goal is to cut the energy AI systems burn by simply moving data back and forth.
The bottleneck in AI's query path
Most computers still rely on von Neumann architecture, a decades-old blueprint that keeps memory and processing separate. Every AI query requires electricity to travel through a maze of wires between these two components. That trip, not the math itself, drives up energy costs.
For everyday users, this translates into higher subscription costs, slower response times, new data centers appearing near communities, and strain on regional power grids. As AI models grow larger, the bottleneck worsens.
Why light changes the equation
"Electronics are ideal for the precise calculations needed during AI training and complex computations, while photonics excel at moving vast amounts of data quickly during inference," Hassan said. "This ability to switch between the two based on the task is what makes this approach so innovative and exciting."
Light-based computing moves data as light rather than electrical current. Multiple data streams can travel together as different colors of light using wavelength-division multiplexing. Hassan's team pairs this with a 3D-stacked chip design that places memory and computing layers vertically, shortening the distance data must travel in an approach called near-memory computing.
This differs from commercial efforts at NVIDIA, Intel, and Micron, which Hassan said are exploring photonics mainly as a data interconnect rather than a first-class part of the architecture. "AI model sizes and the power they require have grown much faster than what traditional chip scaling can handle," Hassan said.
The work sits at the intersection of Generative AI and LLM infrastructure demands and hardware efficiency research. If 3DPFLOPS meets its goals, the same near-memory efficiency gains could let phones, wearables, and other devices run more AI features locally while saving battery life and reducing dependence on distant servers.
Building regional research capacity
Hassan's path to 3DPFLOPS traces back to her doctoral research on power-efficient hardware for wearable biomedical devices. "With the rapid rise of AI and the widespread construction of data centers across the country, I feel like it's now more important than ever to turn our attention to the architecture of computers themselves," she said.
The team includes co-principal investigators Karthik Srinivasan and Purab Sutradhar, assistant professors with expertise in photonics and memory architecture respectively, along with industry partner Luceda Photonics. The grant will support two existing Boise State courses and fund a new multidisciplinary workshop spanning digital, analog, and photonic computing, with hands-on experience using industry-standard photonic design tools.
Why this matters for science and research professionals
For researchers working with AI for Science & Research, the energy cost of model inference directly affects project budgets, compute availability, and institutional infrastructure decisions. Hardware approaches like 3DPFLOPS address a constraint that software optimization alone cannot solve: the physical distance between memory and processing. Tracking progress in near-memory computing and photonic accelerators will help research teams anticipate when larger models or faster inference become affordable within existing power envelopes.
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